1. Field of the Invention
This invention generally relates to communications and, more particularly, to a system and method for the communication of a high-speed serial stream over multiple slower physical interfaces.
2. Description of the Related Art
XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10 GbE). XAUI is a concatenation of the Roman numeral X, meaning ten, and the initials of Attachment Unit Interface. The XGMII Extender, which is composed of an XGXS at the MAC end, an XGXS at the PHY end and a XAUI between them, is used to extend the operational distance of the XGMII and to reduce the number of interface signals. Applications include extending the physical separation possible between MAC and PHY components in a 10 Gigabit Ethernet system distributed across a circuit board.
The XAUI interface is a simple, commonly used, standardized, and well understood protocol, with many different verification environments available. An enhanced version of the interface, referred to herein as XAUI-like, uses the same protocol as XAUI but can run at frequencies higher that the ones specified for XAUI (3.125 Gb/s).
XAUI uses simple signal mapping to the XGMII, and has independent transmit and receive data paths. Four lanes convey the XGMII 32-bit data and control per direction. Differential signaling is used with a low voltage swing (1600 mVpp), and 8b/10b encoding. A self-timed interface allows jitter control to the physical coding sublayer (PCS). XAUI shares technology with other 10 gigabit per second (Gb/s) interfaces and functionality with other 10 Gb/s Ethernet blocks.
The optional XGMII Extender can be inserted between the Reconciliation Sublayer and the PHY (physical layer) to transparently extend the physical reach of the XGMII and reduce the interface pin count from 72 to 16. The XGMII is organized into four lanes with each lane conveying a data octet or control character on each edge of the associated clock. The source XGXS converts bytes on an XGMII lane into a self clocked, serial, 8b/10b encoded data stream. Each of the four XGMII lanes is transmitted across one of the four XAUI lanes.
The source XGXS converts XGMII Idle control characters (interframe) into an 8b/10b code sequence. The destination XGXS recovers clock and data from each XAUI lane and deskews the four XAUI lanes into the single-clock XGMII. The destination XGXS adds to, or deletes from the interframe as needed for clock rate disparity compensation prior to converting the interframe code sequence back into XGMII Idle control characters. The XGXS uses the same code and coding rules as the 10 GBASE-X PCS and PMA specified in Clause 48 of the IEEE 802.3 Specification. Each of the 4 Receive and Transmit lanes operates at a rate of 3.125 Gbs/s.
Capabilities have been built into XAUI to overcome the inter-lane signal-skewing problems using a type of automatic de-skewing. Signals can be launched at the transmitter end of a XAUI line without precisely matching the routing of the four lanes, and the signals will be automatically de-skewed at the receiver.
The implementation of XAUI as an optional XGMII Extender is primarily intended as a chip-to-chip (integrated circuit to integrated circuit) interface implemented with traces on a printed circuit board. Where the XGMII is electrically limited to distances of approximately 2 to 3 inches, the XGMII Extender allows distances up to approximately 25 inches.
The XGMII Extender supports the 10 Gb/s data rate of the XGMII. The 10 Gb/s MAC data stream is converted into four lanes at the XGMII (by the Reconciliation Sublayer for transmit or the PHY for receive). The byte stream of each lane is 8b/10b encoded by the XGXS for transmission across the XAUI at a nominal rate of 3.125 GBaud. The XGXS at the PHY end of the XGMII Extender (PHY XGXS) and the XGXS at the RS end (DTE XGXS) may operate on independent clocks.
The XGMII Extender is transparent to the Reconciliation Sublayer and PHY device, and operates symmetrically with similar functions on the DTE transmit and receive data paths. The XGMII Extender is logically composed of two XGXSs interconnected with a XAUI data path in each direction. One XGXS acts as the source to the XAUI data path in the DTE transmit path and as the destination in the receive path. The other XGXS is the destination in the transmit path and source in the receive path. Each XAUI data path is composed of four serial lanes. All specifications for the XGMII Extender are written assuming conversion from XGMII to XAUI and back to XGMII, but other techniques may be employed provided that the result is that the XGMII Extender operates as if all specified conversions had been made. One example of this is the use of the optional XAUI with the 10 GBASE-LX4 8b/10b PHY, where the XGXS interfacing to the Reconciliation Sublayer provides the PCS and PMA functionality required by the PHY. An XGXS layer is not required at the PHY end of the XAUI in this case. However, means may still be required to remove jitter introduced on the XAUI in order to meet PHY jitter requirements.
Other conventional protocols used to carry frames (or framed data) include, but are not limited to, the following protocols that have 10G embodiments: SFI (SFI-4.x), SFI-5S, TFI (TFI-4.x), and XFI. Other 10G protocols and other non-10G protocols are also used to carry frames (or framed data).
There is standardization effort in progress within IEEE for 40GE and 100GE LAN, but the standard is not expected to be published until June 2010. There is also a standardization effort within ITU-T for mapping 40GE clients into ODU3 and 100GE into ODU4, but this is also not complete yet.
With the demand for more bandwidth growing internationally, and the higher speed Ethernet protocols such as 40GE and 100GE under standardization, Telecom providers are looking for ways to transport these high speed bit framed protocols over OTN networks. OTN (Optical Transport Network) has become one of the dominant technologies for transporting a wide variety of clients over distances in the excess of 100 Km.
In order for network carriers to transport the equivalent of 40 Gb/s Ethernet today, they need to use four 10 Gigabit Ethernet (10GE) sets of systems, each system integrating a 10GE MAC, PCS and PMA separate layer, as well as 4 OTN Framer/Mappers with independent NMS (Network Management System) functions. It also limits the maximum rate for each MAC stream to ˜10 Gb/s.
It would be advantageous if framed or non-framed data could be carried through high data rate Ethernet protocols using existing XAUI-like interfaces.